The present invention relates to a method and/or architecture for implementing read only memory (ROM) code generally and, more particularly, to a method and/or architecture for implementing ROM code compression and uncompression.
Conventional methods and/or architectures for storing code in read only memories (ROMs) and flash memories typically store the code in uncompressed form. As a result, conventional ROMs and flash memories that are implemented to store code have one or more of the following deficiencies: (i) excessive die size, (ii) excessive cost, (iii) code storage is not optimized, (iv) a limited amount of code can be stored, and/or (v) circuitry and/or products that implement the code have limited features.
It would be desirable to have a method and/or architecture for implementing ROM (and flash memory) code storage compression and/or uncompression that (i) reduces the size and/or cost of ROM configured for storing the ROM code and (ii) maintains random, single cycle ROM access.
The present invention concerns an apparatus comprising one or more memory circuits and an uncompress circuit. The one or more memory circuits may be configured to (a) store (i) a number of compressed code words and (ii) a number of delta words and (b) provide random access to the compressed code words in response to an address. The compressed code words may be losslessly compressed in response to (i) a number of uncompressed code words and (ii) the delta words. The delta words generally comprise bit strings that may be configured to minimize a size of the one or more memory circuits when deleted from the uncompressed code words. The uncompress circuit may be configured to losslessly uncompress the compressed code words in response to the delta words.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a read only memory (ROM) code compression and/or uncompression (or decompression) that may (i) provide scalable ROM code (ii) adapt to a target ROM size and/or a compression level target, (iii) optimize code compression, (iv) be implemented in software, firmware, hardware and/or any appropriate combination thereof, (v) be based on predetermined user constraints (e.g., memory size, compressed word format options, compressed word memory entry stuffing options, hardware performance architecture options, etc.), (vi) optimize the number of compression word entries, (vii) implement a lookup table (LUT) ROM for any location mapping to any ROM word, (viii) implement a word format that may provide for multiple compressed code entries to be implemented in a given word location, (ix) be broadly applicable (e.g., may be implemented via on-chip ROM, off-chip ROM, a combination of on-chip and off-chip ROM, and/or multiple stages of ROM), (x) be implemented in application specific integrated circuits (ASICs), customer specific integrated circuits (CSICs), field programmable gate arrays (FPGAs), standard parts, and/or embedded in ROM and/or flash memory devices, (xi) provide a small boot loader to download the compressed ROM code, (xii) provide a compressed boot loader in addition to compressed ROM code, (xiii) provide a programmed delta word base and a multiplexer control and a decoder circuit, (xiv) be scalable to different ROM word size and depth as well as any appropriate number of delta words, (xv) provide random access to the ROM code in the compressed format, (xvi) provide minimal and fast hardware to uncompress the ROM code words via known delta words (base) that are available in memory and multiple parallel absolute functions, and/or (xvii) maintain single cycle access to the ROM.